ATA8741-PXQW【PDF 97/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

93页 94页 95页 96页 [97页]98页 99页 100页 101页

9140CINDCO02/10

ATA8741

ture is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output

Compare unit is enabled in the fast PWM mode.

20.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In

non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare

Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while

down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope

operation has lower maximum operation frequency than single slope operation. However, due to

the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor con-

trol applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 20-7 on page 97. The TCNT0 value is in the timing diagram shown as a histogram for

illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM out-

puts. The small horizontal line marks on the TCNT0 slopes represent Compare Matches

between OCR0x and TCNT0.

Figure 20-7. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

CNTn

eriod

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

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